SPC563M60X datasheet(103/128 Pages) STMICROELECTRONICS

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SPC563M64x, SPC563M60x

Electrical characteristics

127

Figure 10. Nexus output timing

tTCYC

Absolute Minimum TCK Cycle Time

100(8)

—ns

tTDC

TCK Duty Cycle

tNTDIS

TDI Data Setup Time

—

tNTDIH

TDI Data Hold Time

—

tNTMSS

TMS Data Setup Time

—

tNTMSH

TMS Data Hold Time

—

tJOV

TCK Low to TDO Data Valid

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing

specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, TA

= TL to TH, and CL = 30 pF with DSC = 0b10.

Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting

(NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute

minimum MCKO period specification.

This may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on the

actual system frequency being used.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less

than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency

being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute

minimum TCK period specification.

This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the

design (system frequency / 4) depending on the actual system frequency being used.

Table 38. Nexus debug port timing(1) (continued)

Symbol

Characteristic

Min. Value Max. Value

Unit

MCKO

MDO

MSEO

EVTO

Output Data Valid

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