L99LDLH32 datasheet(106/142 Pages) STMICROELECTRONICS

106 / 142 page

FTP and RAM memory mapping

L99LDLH32

106/142

DS12879 Rev 6

7.1.19

FTP status 1

Figure 77. FTP status register #1

2TSD

Thermal Shutdown Status bit:

0: TJ < T_TSD - T_TSD_HYS, thermal shutdown not active,

device not in autorestart thermal cycling

1: TJ > T_TSD - T_TSD_HYS, thermal shutdown active,

device in autorestart thermal cycling

Not used

PG_NOT_VPRE_REG(1)

Power Good Threshold Status bit VPRE_REG:

0: VPRE_REG < PG_TH_VPRE_REG, Power good threshold

reached on VPRE_REG

1: VPRE_REG > PG_TH_VPRE_REG, Power good threshold

not reached on VPRE_REG

1. Whenever PG_NOT_VPRE_REG is set, the application shall temporarily deactivate the Pre-regulator control algorithm, by

two consecutive UNICAST WRITE frames to disable and enable VREF_PRE_REG bit (bit 22 of Chapter 7.1.6).

Table 59. Device status 3 field description (continued)

Bit

Name

Default

Description

Address 2Fh

Access

Burst Read from 2Ch

Data Byte 3

Data Byte 2

Data Byte 1

Data Byte 0

bit

bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

—

PWM_DUTY_ALL_ALT

Table 60. FTP status 1 field description

Bit

Name

Default

Description

31-22

Not used

21-20

POR_DELAY

Power on Reset Delay Time t_POR_DELAY; delay time

before activating outputs in Fail Safe / Stand alone mode

after POR

00: 0 ms

01: 25 ms

10: 50 ms

11: 100 ms

19-18

WD_CONF

Watchdog timeout period tWD

00: 50 ms

01: 100 ms

10: 200 ms

11: 25 ms

L99LDLH32 Datasheet(PDF) 106 Page - STMicroelectronics

L99LDLH32 Datasheet(HTML) 106 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL