XIO2001IZWS.B datasheet(38/145 Pages) TI2

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Figure 8-14 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The serial-bus

protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are transferred.

The number of transferred data bytes is controlled by the bridge master. After each data byte, the bridge master

issues acknowledge (logic low) if more data bytes are requested. The transfer ends after a bridge master no

acknowledge (logic high) followed by a stop condition.

Figure 8-14. Serial-Bus Protocol – Multibyte Read

Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the three

previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control bit is

asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol. This

feature allows the system designer a second serial-bus protocol option when selecting external EEPROM

devices.

8.3.8.3 Serial-Bus EEPROM Application

The registers and corresponding bits that are loaded through the EEPROM are provided in Table 8-8.

Table 8-8. EEPROM Register Loading Map

SERIAL EEPROM WORD

ADDRESS

BYTE DESCRIPTION

00h

PCI-Express to PCI bridge function indicator (00h)

01h

Number of bytes to download (25h)

02h

PCI 44h, subsystem vendor ID, byte 0

03h

PCI 45h, subsystem vendor ID, byte 1

04h

PCI 46h, subsystem ID, byte 0s

05h

PCI 47h, subsystem ID, byte 1s

06h

PCI D4h, general control, byte 0

07h

PCI D5h, general control, byte 1

08h

PCI D6h, general control, byte 2

09h

PCI D7h, general control, byte 3

0Ah

PCI D8h, clock control

0Bh

PCI D9h, clock mask

0Ch

Reserved—no bits loaded

0Dh

PCI DCh, arbiter control

0Eh

PCI DDh, arbiter request mask

0Fh

PCI C0h, control and diagnostic register, byte 0

10h

PCI C1h, control and diagnostic register, byte 1

11h

PCI C2h, control and diagnostic register, byte 2

12h

PCI C3h, control and diagnostic register, byte 3

13h

PCI C4h, control and diagnostic register, byte 0

14h

PCI C5h, control and diagnostic register, byte 1

15h

PCI C6h, control and diagnostic register, byte 2

15h

PCI C6h, control and diagnostic register, byte 2

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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