XIO2001IZWS.B datasheet(59/145 Pages) TI2

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8.4.31 Capability ID Register

This read-only register identifies the linked list item as the register for Subsystem ID and Subsystem Vendor ID

capabilities. The register returns 0Dh when read.

PCI register offset:

40h

Read-only

Default value:

0Dh

BIT NUMBER

RESET STATE

8.4.32 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This

PCI register offset:

41h

Read-only

Default value:

48h

BIT NUMBER

RESET STATE

8.4.33 Subsystem Vendor ID Register

This register, used for system and option card identification purposes, may be required for certain operating

systems. This read-only register is initialized through the EEPROM and can be written through the subsystem

access register at offset D0h. This register is reset by a PCI Express reset ( PERST), a GRST, or the internally-

generated power-on reset.

PCI register offset:

44h

Read-only

Default value:

0000h

BIT NUMBER

RESET STATE

8.4.34 Subsystem ID Register

This register, used for system and option card identification purposes, may be required for certain operating

systems. This read-only register is initialized through the EEPROM and can be written through the subsystem

alias register. This register is reset by a PCI Express reset ( PERST), a GRST, or the internally-generated

power-on reset.

PCI register offset:

46h

Read-only

Default value:

0000h

BIT NUMBER

RESET STATE

8.4.35 Capability ID Register

This read-only register identifies the linked list item as the register for PCI Power Management ID Capabilities.

The register returns 01h when read.

PCI register offset:

48h

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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