XIO2001IZWS.B datasheet(74/145 Pages) TI2

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Read-only, Read/Write

Default value:

00XXh

BIT NUMBER

RESET STATE

Table 8-44. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:5

RSVD

Reserved. Returns 000h when read.

4(1)

GPIO4_DATA

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of

GPIO4 when in output mode.

3(1)

GPIO3_DATA

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of

GPIO3 when in output mode.

2(1)

GPIO2_DATA

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of

GPIO2 when in output mode.

1(1)

GPIO1_DATA

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of

GPIO1 when in output mode.

0(1)

GPIO0_DATA

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of

GPIO0 when in output mode.

(1)

These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

8.4.62 TL Control and Diagnostic Register 0

The contents of this register are used for monitoring status and controlling behavior of the bridge. See Table

8-45 for a complete description of the register contents. It is recommended that all values within this register be

left at the default value. Improperly programming fields in this register may cause interoperability or other

problems.

PCI register offset:

C0h

Read/Write

Default value:

0000 0001h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 8-45. Control and Diagnostic Register 0 Description

BIT

FIELD NAME

ACCES

DESCRIPTION

31:24(1) PRI_BUS_NUM

This field contains the captured primary bus number.

23:19(1) PRI_DEVICE_ NUM

This field contains the captured primary device number.

ALT_ERROR_REP

Alternate Error Reporting. This bit controls the method that the XIO2001 uses for error

reporting.

0 =

1 =

Advisory Non-Fatal Error reporting supported (default)

Advisory Non-Fatal Error reporting not supported

17:16

RSVD

Reserved. Returns 00b when read.

15:14(1) RSVD

Reserved. Bits 15:14 default to 00b. If this register is programmed via EEPROM or another

mechanism, the value written into this field must be 00b.

13:12

RSVD

Reserved. Returns 00b when read.

11:7(1)

RSVD

Reserved. Bits 11:7 default to 00000b. If this register is programmed via EEPROM or

another mechanism, the value written into this field must be 00000b.

6:3

RSVD

Reserved. Returns 0h when read.

2(1)

CFG_ACCESS

_MEM_REG

Configuration access to memory-mapped registers. When this bit is set, the bridge allows

configuration access to memory-mapped configuration registers.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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