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XIO2001IZWS.B Datasheet(PDF) 77 Page - Texas Instruments |
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XIO2001IZWS.B Datasheet(HTML) 77 Page - Texas Instruments |
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77 / 145 page ![]() 8.4.65 Subsystem Access Register The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 44h and 46h. See Table 8-48 for a complete description of the register contents. PCI register offset: D0h Register type: Read/Write Default value: 0000 0000h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 8-48. Subsystem Access Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:16(1) SubsystemID RW Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI offset 46h (see Section 8.4.34). 15:0(1) SubsystemVendorID RW Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID register at PCI offset 44h (see Section 8.4.33). (1) These bits are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset. www.ti.com XIO2001 SCPS212J – MAY 2009 – REVISED JANUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: XIO2001 |
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