XIO2001IZWS.B datasheet(79/145 Pages) TI2

79 / 145 page

Table 8-49. General Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

22:20(1) POWER_OVRD

Power override. This bit field determines how the bridge responds when the slot power limit is

less than the amount of power required by the bridge and the devices behind the bridge.

000 = Ignore slot power limit (default).

001 = Assert the PWR_OVRD terminal.

010 = Disable secondary clocks selected by the clock mask register.

011 = Disable secondary clocks selected by the clock mask register and assert the

PWR_OVRD terminal.

100 = Respond with unsupported request to all transactions except for configuration

transactions (type 0 or type 1) and set slot power limit messages.

101,110,

111 =

Reserved

19(1)

READ_PREFETC

H_DIS

Read Prefetch Disable. This bit is used to control the pre-fetch functionality on PCI memory read

transactions.

0 = Memory read, memory read line, and memory read multiple will be treated as

prefetchable reads (default)

1 = Memory read line, and memory read multiple will be treated as pre-fetchable reads.

Memory read will not be prefetchable. No auto-prefetch reads will be made for these

requests.

18:16(1) L0s_LATENCY

L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the

L0s state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 74h, see

Section 8.4.50).

000 =

001 =

010 =

011 =

100 =

101 =

110 =

111 =

Less than 64 ns (default)

64 ns up to less than 128 ns

128 ns up to less than 256 ns

256 ns up to less than 512 ns

512 ns up to less than 1 μs

1 μs up to less than 2 μs

2 μs to 4 μs

More than 4 μs

15:13(1) L1_LATENCY

L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the

L1 state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 74h, see

Section 8.4.50).

000 =

001 =

010 =

011 =

100 =

101 =

110 =

111 =

Less than 1 μs (default)

1 μs up to less than 2 μs

2 μs up to less than 4 μs

4 μs up to less than 8 μs

8 μs up to less than 16 μs

6 μs up to less than 32 μs

32 μs to 64 μs

More than 64 μs

12(1)

VC_CAP_EN

VC Capability Structure Enable. This bit is hardwired to 0b indicating that the VC Capability

structure is permanently disabled.

11(2)

BPCC_E

Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are

stopped when the XIO2001 is placed in the D3 state. It is assumed that if the secondary bus

clocks are required to be active, that a reference clock continues to be provided on the PCI

Express interface.

0 = Secondary bus clocks are not stopped in D3 (default)

1 = Secondary bus clocks are stopped on D3

10(2)

BEACON_ENABL

Beacon enable. This bit controls the mechanism for waking up the physical PCI Express link

when in L2.

0 = WAKE mechanism is used exclusively. Beacon is not used (default)

1 = Beacon and WAKE mechanisms are used

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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