XIO2001IZWS.B datasheet(46/145 Pages) TI2

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8.4.5 Status Register

The status register provides information about the PCI Express interface to the system. See Table 8-13 for a

complete description of the register contents.

PCI register offset:

06h

Read-only, Read/Clear

Default value:

0010h

BIT NUMBER

RESET STATE

Table 8-13. Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

PAR_ERR

RCU

Detected parity error. This bit is set when the PCI Express interface receives a poisoned

TLP. This bit is set regardless of the state of bit 6 (PERR_ENB) in the command register

(offset 04h, see Section 8.4.4).

0 = No parity error detected

1 = Parity error detected

SYS_ERR

RCU

Signaled system error. This bit is set when the bridge sends an ERR_FATAL or

ERR_NONFATAL message and bit 8 (SERR_ENB) in the command register (offset 04h,

see Section 8.4.4) is set.

0 = No error signaled

1 = ERR_FATAL or ERR_NONFATAL signaled

MABORT

RCU

Received master abort. This bit is set when the PCI Express interface of the bridge

receives a completion-with-unsupported-request status.

0 = Unsupported request not received on the PCI Express interface

1 = Unsupported request received on the PCI Express interface

TABORT_REC

RCUT

Received target abort. This bit is set when the PCI Express interface of the bridge receives

a completion-with-completer-abort status.

0 = Completer abort not received on the PCI Express interface

1 = Completer abort received on the PCI Express interface

TABORT_SIG

RCUT

Signaled target abort. This bit is set when the PCI Express interface completes a request

with completer abort status.

0 = Completer abort not signaled on the PCI Express interface

1 = Completer abort signaled on the PCI Express interface

10:9

PCI_SPEED

DEVSEL timing. These bits are read-only 00b, because they do not apply to PCI Express.

DATAPAR

RCU

Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset

04h, see Section 8.4.4) is set and the bridge receives a completion with data marked as

poisoned on the PCI Express interface or poisons a write request received on the PCI

Express interface.

0 = No uncorrectable data error detected on the primary interface

1 = Uncorrectable data error detected on the primary interface

FBB_CAP

Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express

device and is hardwired to 0b.

RSVD

Reserved. Returns 0b when read.

66MHZ

66-MHz capable. This bit does not have a meaningful context for a PCI Express device

and is hardwired to 0b.

CAPLIST

Capabilities list. This bit returns 1b when read, indicating that the bridge supports

additional PCI capabilities.

INT_STATUS

Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b

since the bridge does not generate any interrupts internally.

2:0

RSVD

Reserved. Returns 000b when read.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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