XIO2001IZWS.B datasheet(71/145 Pages) TI2

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Table 8-40. Link Status Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

SCC

Slot clock configuration. This bit indicates that the bridge uses the same physical reference

clock that the platform provides on the connector. If the bridge uses an independent clock

irrespective of the presence of a reference on the connector, then this bit must be cleared.

0 = Independent 125-MHz reference clock is used

1 = Common 100-MHz reference clock is used

Link training. This bit has no function and is read-only 0b.

Retrain link. This bit has no function and is read-only 0b.

9:4

NLW

Negotiated link width. This field is read-only 00 0001b indicating the lane width is x1.

3:0

Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.

8.4.56 Serial-Bus Data Register

The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this

cycle. When reading data from the serial bus, this register contains the data read after bit 5 (REQBUSY) of the

serial-bus control and status register (offset B3h, see Section 8.4.59) is cleared. This register is reset by a PCI

Express reset ( PERST), a GRST, or the internally-generated power-on reset.

PCI register offset:

B0h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

8.4.57 Serial-Bus Word Address Register

The value written to the serial-bus word address register represents the word address of the byte being read

from or written to the serial-bus device. The word address is loaded into this register prior to writing the serial-

bus slave address register (offset B2h, see Section 8.4.58) that initiates the bus cycle. This register is reset by a

PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset.

PCI register offset:

B1h

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

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XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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