XIO2001IZWS.B datasheet(10/145 Pages) TI2

10 / 145 page

Pin Functions

SIGNAL

ZWS

BALL

NO.

ZAJ

BALL NO.

PNP

PIN NO.

I/O

TYPE

CELL

TYPE

CLAMP

RAIL

EXTERNAL

PARTS

DESCRIPTION

PCI EXPRESS

CLKREQ

D11

CMOS

VDD_33_

COMBIO

–

Clock request. When asserted low, requests

upstream device start clock in cases where clock

may be removed in L1.

Note: Since CLKREQ is an open-drain output

buffer, a system side pullup resistor is required.

PERST

H11

CMOS

VDD_33_

COMBIO

–

PCI Express reset input. The PERST signal

identifies when the system power is stable and

generates an internal power on reset.

Note: The PERST input buffer has hysteresis.

REFCLK125_SEL

B13

A13

CMOS

VDD_33

Pullup or

pulldown

resistor

Reference clock select. This terminal selects the

reference clock input.

0 = 100-MHz differential common reference clock

used.

1 = 125-MHz single-ended, reference clock used.

REFCLK+

C13

HS DIFF

VDD_33

–

Reference clock. REFCLK+ and REFCLK–

comprise the differential input pair for the 100-

MHz system reference clock. For a single-ended,

125-MHz system reference clock, use the

REFCLK+ input.

REFCLK–

C12

B13

HS DIFF

VDD_33

Capacitor for

VSS for

single-ended

node

Reference clock. REFCLK+ and REFCLK–

comprise the differential input pair for the 100-

MHz system reference clock. For a single-ended,

125-MHz system reference clock, attach a

capacitor from REFCLK– to VSS.

REF0_PCIE

REF1_PCIE

K12

K13

M13

L13

I/O

BIAS

–

External

resistor

External reference resistor + and – terminals for

setting TX driver current. An external resistance

of 14,532-Ω is connected between REF0_PCIE

and REF1_PCIE terminals. To eliminate the need

for a custom resistor, two series resistors are

recommended: a 14.3-kΩ, 1% resistor and a 232-

Ω, 1% resistor.

RXP

RXN

E13

E12

E13

D13

HS DIFF

VSS

–

High-speed receive pair. RXP and RXN comprise

the differential receive pair for the single PCI

Express lane supported.

TXP

TXN

G13

G12

H13

G13

HS DIFF

OUT

VDD_15

Series

capacitor

High-speed transmit pair. TXP and TXN comprise

the differential transmit pair for the single PCI

Express lane supported.

WAKE

M13

L12

CMOS

VDD_33_

COMBIO

–

Wake is an active low signal that is driven low to

reactivate the PCI Express link hierarchy’s main

power rails and reference clocks.

Note: Since WAKE is an open-drain output buffer,

a system side pullup resistor is required.

XIO2001

SCPS212J – MAY 2009 – REVISED JANUARY 2021

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