Symbol

I/O voltage

I/O

Description

Ball

Reset state

SFC_SIO5

IO ring1

I/O

Serial flash memory controller data IO 5

M2

Hi-Z/PD

SFC_SIO6

IO ring1

I/O

Serial flash memory controller data IO 6

T4

Hi-Z/PD

SFC_SIO7

IO ring1

I/O

Serial flash memory controller data IO 7

P1

Hi-Z/PD

Note:

These interface IOs are alternate functions A of GPIOs.

3.9

SSP

STA8135G has one synchronous serial ports (SSPs). The SSP is a master or slave interface that enables

synchronous serial communication with slave or master peripherals having one of the following:

•

Serial peripheral interface bus standards

•

Synchronous serial protocol bus standards

•

Micro-wire interface bus standards

•

Unidirectional interface

In both master and slave configurations, the SSP has the following features:

•

Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep transmit FIFO

•

Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location deep receive FIFO

•

Programmable data frame size from 4 to 32 bits

•

Programmable clock bit rate and pre-scaler

•

Programmable clock phase and polarity in SPI mode

•

Support for direct memory access (DMA)

3.10

UART

The UARTx performs serial-to-parallel conversion on data asynchronously received from a peripheral device on

UARTx_RX pin, and parallel-to-serial conversion on data written by CPU for transmission on UARTx_TX pin. The

transmit and receive paths are buffered with internal FIFO memories allowing up to 64 data byte for transmission,

and 64 data byte with 4-bit status (break, frame, parity, and overrun) to receive. FIFOs may be burst-loaded or

emptied by the system processor or DMA, from one to sixteen words per transfer.

3.11

Watchdog timer (WDT)

Watchdog timer (WDT) provides a way of recovering from software crashes. The watchdog clock is used to

generate a regular interrupt (Irq_wdt), depending on a programmed value.

The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt remains unserviced

for the entire programmed period. The WDT is counting down at a fixed frequency of 32.768 kHz.

The watchdog timer peripheral can be used as free-running timer or as watchdog to resolve processor

malfunctions due to hardware or software failures.

Feature set overview:

•

16-bit down counter

•

8-bit clock pre-scaler

•

Safe reload sequence

•

Free-running timer mode

•

End of counting interrupt generation

STA8135G

General description

DS14788 - Rev 1

page 16/41