STA8135G datasheet(4/41 Pages) STMICROELECTRONICS

4 / 41 page

Block diagram and pin description

2.1

Block diagram

Figure 1. STA8135G block diagram

GNSS

CPU

EMI

Connectivity

PMU

Always on Domain

G5 RFIP

System

G5 Base Band

Antenna Sensing

DMA

Interrupt Control

Watchdog

Timers

Boot

UART x 3

GPIO

Serial Flash SFC

LDO Core

LDO RF

LDO Backup

Bandgap, Bias,

High-Low Voltage

Detectors

256 byte Backup RAM

Real Time Clock

32kHz Oscillator

Power, Reset, Clock

Controller

ARM Cortex M7

TCM RAM

Multi Mode SPI

Dual Band

External RF Port

I2C

Synch Serial Port

USB

Security

Secure Core

OTFDEC

OTP SAFMEM

2x 10bit ADC

eRAM

256kByte

Temp Sense

LDO 3.3V to 1.8V

SDMMC

CAN x 2

Hyperbus

2.2

Package

TFBGA160 balls with 7x11x1.2 mm body size and 0.65 mm ball pitch.

2.3

Ball list

Note:

All balls have alternate functionalities, which can be selected by relevant registers.

Table 1. Power supply pins

Symbol

I/O voltage

I/O

Description

Ball

VRF_IN

1.62 to 3.6 V PWR LDO RF power input - IO ring RF

M10

VRF_OUT

1.2 V

PWR LDO RF power output

N10

VCC_LNA

1.2 V

PWR LNA power input

T10

VCC_PLL

1.2 V

PWR RF VCC power input

VBK_IN(1)

1.62 to 3.6 V PWR LDO backup power input - IO ring 0

VBK_OUT

1.2 V

PWR LDO backup power output

VCORE_IN

1.62 to 3.6 V PWR LDO core power input

F3, P3

VDD_EXT_REG

1.2 V

PWR LDO core power output

F1, N4, N7, R2, R3

VIO2_IN

3 to 3.6 V

PWR LDO IO ring 2 power input - IO ring 2

G1, H1, J10

VIO1_EXT

1.72 to 1.98 V

3 to 3.6 V

PWR LDO IO ring 1 power output or IO ring 1 input

M3, N3, P2, T2

STA8135G

Block diagram and pin description

DS14788 - Rev 1

page 4/41

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