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STA8135G Datasheet(PDF) 29 Page - STMicroelectronics |
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STA8135G Datasheet(HTML) 29 Page - STMicroelectronics |
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29 / 41 page ![]() 4.6 Power up timing sequence Figure 7. Power up timing diagram VBK_IN VCORE/VDD_EXT_REG Other supplies RESETn On-chip ring osc tRiOscVCOREIN_On tVCOREIN_On tVSupply_On tRESETn tRiOscRESETn Table 26. Power up timing data Symbol Condition Min. Max. Unit Comment tVCORE_IN_On VBK_IN > 1.62 V 0 (1) - ms Time from the power-on of VBK_IN to the power-on of VCORE_IN or VDD_EXT_REG tVSupply_On VBK_IN > 1.62 V 0 (2) - ms Time from the power-on of VBK_IN to the power-on of other supplies tRESETn VBK_IN > 1.62 V 4 - ms Time from the power-on of VBK_IN to RESETn going high tRiOscRESETn VCORE_IN > 1.62 V or VDD_EXT_REG > 1.14 V 0.5 - ms Time from RESETn going high to the on-chip ring oscillator start up tRiOscVCOREIN_On RESETn = high 0.5 - ms Time from VCORE or VDD_EXT_REG applied to the on- chip ring oscillator start up 1. The simultaneous power-on of VBK_IN and VCORE_IN or VDD_EXT_REG is allowed and tested. 2. The simultaneous power-on of VBK_IN and other supplies is allowed and tested 4.7 Digital interface AC timing characteristics Figure 8. Clock block diagram 1 2 3 TOdly TIS TIH CLK period STA8135G Electrical specifications DS14788 - Rev 1 page 29/41 |
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