STA8135G datasheet(30/41 Pages) STMICROELECTRONICS

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Table 27. Clock data

Symbol

Comment

CLK period

Clock time period

tOdly

Output data delay from rising clock edge, unless differently specified

tIS

Input data setup time to rising clock edge, unless differently specified

tIH

Input data hold time from rising clock edge, unless differently specified

4.7.1

SQIO

Table 28. SQIOSDR mode (feedback mode)

Type

Symbol

Min.

Max.

Unit

Cload

Notes

Clock

CLK freq.

78.5

MHz

25 pF

CLK period

12.74

CLK duty cycle

Input

TIS

0.5

TIH

2.5

Output

Todly

-2.5

2.4

25 pF

Note:

Specified by design, not tested in production.

Table 29. SQIODTR mode (DQS mode for flash memory read operations)

Type

Symbol

Min.

Max.

Unit

Cload

Notes

Clock

CLK freq.

MHz

25 pF

Flash memory clock frequency

CLK period

15.38

CLK duty cycle

Input

TIS

TIH

Output

Todly

-1.25

1.8

25 pF

Note:

Specified by design, not tested in production.

4.7.2

SPI

Table 30. SPI (controller mode)

Type

Symbol

Min.

Max.

Unit

Cload

Notes

Clock

CLK freq.

19.625

MHz

25 pF

CLK period

50.95

CLK duty cycle

Input

TIS

TIH

Output

Todly

25 pF

Note:

Specified by design, not tested in production.

STA8135G

Electrical specifications

DS14788 - Rev 1

page 30/41

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