JS48F4400P0P3C0 datasheet(48/139 Pages) NUMONYX

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Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

309823-10

7.0

NOR Flash AC Characteristics

Timing symbols used in the timing diagrams within this document conform to the

following conventions:

Note:

Exceptions to this conventions include tACC and tAPA. tACC is a generic timing symbol

that refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and

tGLQV (whichever is satisfied last) of the flash device. tAPA is specified in the flash

device datasheet, and is the address-to-data delay for subsequent page-mode reads.

7.1

AC Test Conditions

Note:

AC test inputs are driven at VCCQ for Logic ‘1’ and 0.0 V for Logic ‘0’. Input/output timing begins and ends at VCCQ/2.

Figure 17: Timing Symbol Notation Convention

Table 16: Codes for Timing Signals and Timing States

Signal

Code

State

Code

Address

High

Data - Read

Low

Data - Write

High-Z

Chip Enable (CE#)

Low-Z

Output Enable (OE#)

Valid

Write Enable (WE#)

Invalid

Address Valid (ADV#)

—

Reset (RST#)

—

Clock (CLK)

—

WAIT

—

Figure 18: AC Input/Output Reference Waveform

L Q V

Source Signal

Target State

Source State

Target Signal

CCQ

CC Q

CCQ

Te st Points

Input

Output

RISE/FALL

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