JS48F4400P0P3C0 datasheet(28/139 Pages) NUMONYX

28 / 139 page

Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

309823-10

OE#

Input

OUTPUT ENABLE: Flash- and SRAM-specific signal; low-true input.

When low, OE# enables the output drivers of the selected flash or SRAM die. When high, OE#

disables the output drivers of the selected flash or SRAM die and places the output drivers in

High-Z.

F-RST#

Input

FLASH RESET: Flash-specific signal; low-true input.

When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables

normal operation.

F-WAIT

Output

FLASH WAIT: Flash -specific signal; configurable-true output.

When asserted, F-WAIT indicates invalid output data. F-WAIT is driven whenever F-CE# and

OE# are low. F-WAIT is High-Z whenever F-CE# or OE# is high.

WE#

Input

WRITE ENABLE: Flash- and SRAM-specific signal; low-true input.

When low, WE# enables Write operations for the enabled flash or SRAM die.

D-WE#

Input

LPSDRAM WRITE ENABLE: LPSDRAM-specific signal; low-true input.

D-WE#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-RAS#, define the

LPSDRAM command or operation. D-WE# is sampled on the rising edge of D-CLK.

F-

WP[2:1]#

Input

FLASH WRITE PROTECT: Flash-specific signals; low-true inputs.

When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the Lock-

Down function, enabling locked-down blocks to be unlocked with the Unlock command.

• F-WP1# is dedicated to flash die #1.

• F-WP2# is common to all other flash dies, if present. Otherwise it is RFU.

• For NOR/NAND stacked device, F-WP1# selects all NOR dies; F-WP2# selects all NAND dies.

F-DPD

Input

FLASH DEEP POWER-DOWN: Flash-specific signal; configurable-true input.

When enabled in the ECR, F-DPD is used to enter and exit Deep Power-Down mode.

N-CLE

Input

NAND COMMAND LATCH ENABLE: NAND-specific signal; high-true input.

When high, N-CLE enables commands to be latched on the rising edge of N-WE#.

N-ALE

Input

NAND ADDRESS LATCH ENABLE: NAND-specific signal; high-true input.

When high, N-ALE enables addresses to be latched on the rising edge of N-WE#.

N-RE#

Input

NAND READ ENABLE: NAND-specific signal; low-true input.

When low, N-RE# enables the output drivers of the selected NAND die. When high, N-RE#

disables the output drivers of the selected NAND die and places the output drivers in High-Z.

2, 4

N-RY/BY#

Output

NAND READY/BUSY: NAND-specific signal; low-true output.

When low, N-RY/BY# indicates the NAND is busy performing a read, program, or erase

operation. When high, N-RY/BY# indicates the NAND device is ready.

N-WE#

Input

NAND WRITE ENABLE: NAND-specific signal; low-true input.

When low, N-WE# enables Write operations for the enabled NAND die.

2, 5

D-CKE

Input

LPSDRAM CLOCK ENABLE: LPSDRAM-specific signal; high-true input.

When high, D-CKE indicates that the next D-CLK edge is valid. When low, D-CKE indicates that

the next D-CLK edge is invalid and the selected LPSDRAM die is suspended.

D-BA[1:0]

Input

LPSDRAM BANK SELECT: LPSDRAM-specific input signals.

D-BA[1:0] selects one of four banks in the LPSDRAM die.

D-RAS#

Input

LPSDRAM ROW ADDRESS STROBE: LPSDRAM-specific signal; low-true input.

D-RAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-CAS#, and D-WE#, define the

LPSDRAM command or operation. D-RAS# is sampled on the rising edge of D-CLK.

D-CAS#

Input

LPSDRAM COLUMN ADDRESS STROBE: LPSDRAM-specific signal; low-true input.

D-CAS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-CS#, D-RAS#, and D-WE#, define the

LPSDRAM command or operation. D-CAS# is sampled on the rising edge of D-CLK.

D[2:1]-

CS#

Input

LPSDRAM CHIP SELECT: LPSDRAM-specific signal; low-true input.

When low, D-CS# selects the associated LPSDRAM memory die and starts the command input

cycle. When D-CS# is high, commands are ignored but operations continue.

• D-CS#, together with A[MAX:0], D-BA[1:0], D-CKE, D-RAS#, D-CAS#, and D-WE#, define

the LPSDRAM command or operation. D-CS# is sampled on the rising edge of D-CLK.

• D[2:1]-CS# are dedicated to LPSDRAM die #2 and die #1, respectively, if present.

Otherwise, any unused LPSDRAM chip selects should be treated as RFU.

Table 7:

Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 3 of 4)

Symbol

Type

Signal Descriptions

Notes

JS48F4400P0P3C0 Datasheet(PDF) 28 Page - Numonyx B.V

JS48F4400P0P3C0 Datasheet(HTML) 28 Page - Numonyx B.V

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL