JS48F4400P0P3C0 datasheet(27/139 Pages) NUMONYX

27 / 139 page

April 2008

Datasheet

309823-10

Numonyx™ StrataFlash® Cellular Memory (M18)

F-ADV#

Input

FLASH ADDRESS VALID: Flash-specific signal; low-true input.

During synchronous flash Read operations, the address is latched on the rising edge of F-ADV#,

or on the first rising edge of F-CLK after F-ADV# goes low for devices that support up to 108

MHz, or on the last rising edge of F-CLK after F-ADV# goes low for devices that support up to

133 MHz.

In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#.

A[MAX: 0]

Input

ADDRESS: Global device signals.

Shared address inputs for all memory die during Read and Write operations.

• 4-Gbit: AMAX = A27

• 2-Gbit: AMAX = A26

• 1-Gbit: AMAX = A25

• 512-Mbit: AMAX = A24

• 256-Mbit: AMAX = A23

• 128-Mbit: AMAX = A22

• A[12:0] are the row and A[9:0] are the column addresses for 512-Mbit LPSDRAM.

• A[12:0] are the row and A[8:0] are the column addresses for 256-Mbit LPSDRAM.

• A[11:0] are the row and A[8:0] are the column addresses for 128-Mbit LPSDRAM.

Unused address inputs should be treated as RFU.

AD[15:0]

Input /

Output

ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AAD-Mux flash address and data;

LPSDRAM data.

During AAD-Mux flash Write cycles, AD[15:0] are used to input the upper address, lower

address, and commands or write-data.

During AAD-Mux flash Read cycles, AD[15:0] are used to input the upper address and lower

address, and output read-data.

During LPSDRAM accesses, AD[15:0] are used to input commands and write-data during Write

cycles or to output read-data during Read cycles.

During NAND accesses, AD[7:0] are used to input commands, address-data, or write-data, and

to output read-data.

AD[15:0] are High-Z when the device is deselected or its output is disabled.

F-ADV#

F-ADV2#

Input

FLASH ADDRESS VALID: Flash-specific signal; low-true input.

During a synchronous flash Read operation, the address is latched on the F-ADV# rising edge or

the first F-CLK edge after F-ADV# low in devices that support up to 104 MHz, and on the last

rising F-CLK edge after F-ADV# low in devices that support upto 133 MHz.

During a synchronous flash Read operation, the address is latched on the rising edge of F-ADV#

or the first active F-CLK edge whichever occurs first.

In an asynchronous flash Read operation, the address is latched on the rising edge of F-ADV#.

During AAD-Mux flash accesses, the upper address is latched on the valid edge of F-CLK while

F-ADV2# is low; the lower address is latched on the valid edge of F-CLK while F-ADV# is low.

The upper address is always latched first, followed by the lower address.

Control Signals

F[4:1]-

CE#

Input

FLASH CHIP ENABLE: Flash-specific signal; low-true input.

When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the

associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT

outputs are placed in a High-Z state.

• F1-CE# is dedicated to flash die #1.

• F[4:2]-CE# are dedicated to flash die #4 through #2, respectively, if present. Otherwise,

any unused flash chip enable should be treated as RFU.

• For NOR/NAND stacked device, F1-CE# selects NOR die #1, F2-CE# selects NOR die #2

while F4-CE# selects NAND die #1 and NAND die #2 using virtual chip-select scheme, F3-

CE# selects NAND die #3 if present.

F-CLK

Input

FLASH CLOCK: Flash-specific signal; rising active-edge input.

F-CLK synchronizes the flash with the system clock during synchronous operations.

D-CLK

Input

LPSDRAM CLOCK: LPSDRAM-specific signal; rising active-edge input.

D-CLK synchronizes the LPSDRAM and DDR LPSDRAM with the system clock.

D-CLK#

Input

DDR LPSDRAM CLOCK: DDR LPSDRAM-specific signal; falling active-edge input.

D-CLK# synchronizes the DDR LPSDRAM with the system clock.

Table 7:

Signal Descriptions, x16D Non-Mux/AD-Mux; x16D AA/D-Mux (Sheet 2 of 4)

Symbol

Type

Signal Descriptions

Notes

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