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JS48F4400P0P3C0 Datasheet(PDF) 52 Page - Numonyx B.V

Part # JS48F4400P0P3C0
Description  StrataFlash짰 Cellular Memory
PDF  139 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS48F4400P0P3C0 Datasheet(HTML) 52 Page - Numonyx B.V

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Numonyx™ StrataFlash® Cellular Memory (M18)
Datasheet
April 2008
52
309823-10
7.2.1
Read Timing Waveforms
The following sections show the timing waveforms for Asynchronous and Synchronous
read specifications for Non-Mux and AD-Mux M18 devices.
The Synchronous read timing waveforms apply to both the 108 and 133 MHz devices.
However please note that M18 devices which only support up to 108 MHz need not
meet the R313 to R317 timing specifications.
R104
tVLVH
ADV# pulse width low
7
—
ns
—
R105
tVHVL
ADV# pulse width high
7
—
ns
—
R106
tVHAX
Address hold from ADV# high
5
—
ns
—
R107
tVHGL
ADV# high to OE# low (AD-Mux only)
2
—
ns
—
R108
tAPA
Page address access (non-mux only)
—
15
ns
—
R111
tPHVH
RST# high to ADV# high
30
—
ns
—
Clock Specifications
R200
fCLK
CLK frequency
—
133
MHz
—
R201
tCLK
CLK period
7.5
—
ns
—
R202
tCH/CL
CLK high/low time
0.45
0.55
CLK
Period
4
R203
tFCLK/RCLK CLK fall/rise time
0.3
1.2
ns
—
Synchronous Specifications
R301
tAVCH
Address setup to CLK high
2
—
ns
—
R302
tVLCH
ADV# low setup to CLK high
2
—
ns
—
R303
tELCH
CE# low setup to CLK high
2.5
—
ns
—
R304
tCHQV
CLK to output valid
—
5.5
ns
—
R305
tCHQX
Output hold from CLK high
2
—
ns
—
R306
tCHAX
Address hold from CLK high
2
—
ns
—
R307
tCHTV
CLK high to WAIT valid
—
5.5
ns
—
R311
tCHVL
CLK high to ADV# Setup
2
—
ns
—
R312
tCHTX
WAIT hold from CLK high
2
—
ns
—
R313
tCHVH
ADV# hold from CLK high
2
—
ns
—
R314
tCHGL
CLK to OE# low (AD-Mux only)
2
—
ns
—
R315
tACC
Read access time from address latching clock
96
—
ns
—
R316
tVLVH
ADV# pulse width low for sync reads
1
2
clks
—
R317
tVHCH
ADV# high to CLK high
2
—
ns
—
Notes:
1.
See
Figure 18, “AC Input/Output Reference Waveform” on page 48 for timing measurements and
maximum allowable input slew rate.
2.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3.
Sampled, not 100% tested.
Table 20: AC Read, 133 MHz, VCCQ = 1.7 V to 2.0 V (Sheet 2 of 2)
Nbr.
Symbol
Parameter1
96 ns
Units
Notes
Min
Max



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