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JS48F4400P0P3C0 Datasheet(PDF) 99 Page - Numonyx B.V

Part # JS48F4400P0P3C0
Description  StrataFlash짰 Cellular Memory
PDF  139 Pages
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Manufacturer  NUMONYX [Numonyx B.V]
Direct Link  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

JS48F4400P0P3C0 Datasheet(HTML) 99 Page - Numonyx B.V

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April 2008
Datasheet
309823-10
99
Numonyx™ StrataFlash® Cellular Memory (M18)
Attempting to program an OTP register outside of the OTP register space causes a
program error (SR4 = 1). Attempting to program a locked OTP Register causes a
program error and a lock error (SR4 = 1, SR1 = 1).
To read from any of the OTP registers, first issue the Read Device Information
command. Then read from the desired OTP Register address offset. For additional
details, refer to Section 9.4.3, “Read Device Information” on page 82.
9.11.3
Global Main-Array Protection
Global main-array protection can be implemented by controlling VPP. When
programming or erasing main-array blocks, VPP must be equal to, or greater than VPPL
(min). When VPP is below VPPLK, program or erase operations are inhibited, thus
providing absolute protection of the main array.
Various methods exist for controlling VPP, ranging from simple logic control to off-board
voltage control. Figure 51 shows example VPP supply connections that can be used to
support program/erase operations and main-array protection.
Table 47: Program OTP Register Command Bus Cycles
Command
Setup Write Cycle
Confirm Write Cycle
Address Bus
Data Bus
Address Bus
Data Bus
Program OTP Register
Device Address
00C0h
OTP Register Address Register Data
Figure 51: Example VPP Supply Connections
VCC
VPP
VCC
•
Factory Programming: VPP = VPPH
•
Program/Erase Protection: VPP
≤ VPPLK
≤ 10ΚΩ
VCC
VPP
VCC
•
Program/Erase Enable: PROT# = VIH
•
Program/Erase Protection: PROT# = VIL
PROT#
VCC
VPP
VCC
•
Low-Voltage Programming: VPP = VPPL
-or-
•
Factory Programming: VPP = VPPH
VCC
VPP
VCC
•
Low-Voltage Programming: VPP = VCC
•
Program/Erase Protection: None
VPPH
VPPL
VPPH
VPPL
VPPL



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