JS48F4400P0P3C0 datasheet(72/139 Pages) NUMONYX

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Numonyx™ StrataFlash® Cellular Memory (M18)

Datasheet

April 2008

309823-10

8.1.1

Asynchronous single-word reads

In asynchronous single-word read mode, a single word of data corresponding to the

address is driven onto the data bus after the initial access delay. The address is latched

when ADV# is deasserted. For AD-multiplexed devices, ADV# must be deasserted

before OE# is asserted.

If only asynchronous reads are to be performed, CLK must be tied to a valid VIH or VIL

level, and the WAIT signal can be floated. In addition, for non-multiplexed devices,

ADV# must be tied to ground.

8.1.2

Asynchronous Page Mode (Non-multiplexed devices only)

In asynchronous page mode, sixteen data words are “sensed” simultaneously from the

flash memory array and loaded into an internal page buffer. The buffer word

corresponding to the initial address is driven onto the data bus after the initial access

delay. Subsequent words in the page are output after the page access delay. A[3:0]

bits determine which page word is output during a read operation. A[MAX:4] and ADV#

must be stable throughout the page access.

WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch

the address, or held low throughout the read cycle. CLK is not used for asynchronous

page-mode reads, and is ignored.

8.1.3

Synchronous Burst Mode

Synchronous burst mode is a clock-synchronous read operation that improves the read

performance of flash memory over that of asynchronous reads.

Synchronous burst mode is enabled by programming the Read Configuration Register

(RCR) of the flash memory device. The RCR is also used to configure the burst

parameters of the flash device, including Latency Count, burst length of 8, 16 and

continuous, and WAIT polarity.

Three additional signals are used for burst mode: CLK, ADV#, and WAIT.

The address for synchronous read operations is latched on the ADV# rising edge or the

first rising CLK edge after ADV# low, whichever occurs first for devices that support up

to 108 MHz. For devices that support up to 133 MHz, the address is latched on the last

CLK edge when ADV# is low.

During synchronous read modes, the first word is output from the data buffer on the

rising CLK edge after the initial access latency delay. Subsequent data is output on

rising CLK edges following a tCHQV delay. However, for a synchronous non-array read,

the same word of data will be output on successive rising clock edges until the burst

length requirements are satisfied.

8.1.3.1

WAIT Operation

Upon power up or exit from reset, WAIT polarity defaults to low-true operation (RCR10

= 0). During synchronous reads (RCR15 = 0), WAIT asserts when read data is invalid,

and deasserts when read data is valid. During asynchronous reads (RCR15 = 1), WAIT

is deasserted. During writes, WAIT is High-Z on non-mux devices, and deasserted on

AD-mux devices. Table 28 summarizes WAIT behavior.

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