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JS48F4400P0P3C0 Datasheet(PDF) 80 Page - Numonyx B.V |
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JS48F4400P0P3C0 Datasheet(HTML) 80 Page - Numonyx B.V |
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80 / 139 page ![]() Numonyx™ StrataFlash® Cellular Memory (M18) Datasheet April 2008 80 309823-10 9.3.1 Output Driver Control Output Driver Control enables the user to adjust the device’s output-driver strength of the data I/O bus and WAIT signal. Upon power-up or reset, ECR[2:0] defaults to an output impedance setting of 30 Ohms. To change the output-driver strength, ECR[2:0] must be programmed to the desired setting as shown in Table 34, “Output Driver Control Characteristics”. 9.3.2 Programming the ECR The ECR is programmed by issuing the Program Enhanced Configuration Register command. This is a two-cycle command sequence requiring a Setup command to be issued first, followed by a Confirm command. Bus-write cycles to the flash device between the setup and confirm commands are not allowed—a command sequence error will result. However, flash bus-read cycles between the Setup and Confirm commands are allowed. Table 33: Enhanced Configuration Register Bit Definitions Enhanced Configuration Register Default = 0004h Deep Power Down (DPD) Mode DPD Polarity Reserved Output Driver Control 15 14 13:3 2 1 0 Bit Name Description 15 Deep Power Down (DPD) Mode 0 = DPD Disabled (default) 1 = DPD Enabled 14 DPD Pin Polarity 0= Active Low (default) 1= Active High 13:3 Reserved Write 0 to reserved bits 2:0 Output Driver Control Bits: 2 1 0 001= 1 010= 2 011= 3 100= 4 (default) 101= 5 110= 6 (Other bit settings are reserved) Table 34: Output Driver Control Characteristics Control Bits ECR[2:0] Impedance @ VCCQ/2 (Ohm) Driver Multiplier Load Driven at Same Speed (pF) 001 (1) 90 1/3 10 010 (2) 60 1/2 15 011 (3) 45 2/3 20 100 (4) default 30 1 30 101 (5) 20 3/2 35 110 (6) 15 2 40 |
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