R5F564MFDDFB datasheet(121/162 Pages) RENESAS

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R01DS0173EJ0120 Rev.1.20

Page 121 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.7.11

QSPI

Note 1. tPBcyc: PCLKB cycle

Note 2. We recommend that pins suffixed with the same letter such as -A and -B, indicating grouping of the pins, should be used as a

set. The AC characteristics of the QSPI are measured using the pins from the same group.

Figure 2.63

QSPI Clock Timing

Figure 2.64

Transmit/Receive Timing (CPHA = 0)

Table 2.37

QSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions*2

QSPI

QSPCLK clock cycle

tQScyc

24080

tPBcyc

Figure 2.63

Data input setup time

tSu

6.5

—

Figure 2.64,

Figure 2.65

Data input hold time

tIH

5—

SS setup time

tLEAD

1.5

8.5

tQScyc

SS hold time

tLAG

tQScyc

Data output delay time

tOD

—

10.0

Data output hold time

tOH

–5

—

Successive transmission delay time

tTD

tQScyc

QSPCLK

output

MSB IN

MSB OUT

LSB OUT

IDLE

DATA

LSB IN

DATA

QSSL

output

QSPCLK

CPOL = 0

output

QSPCLK

CPOL = 1

output

QMI,

QIO0 to QIO3

input

QMO,

QIO0 to QIO3

output

tLEAD

tLAG

tSU

tIH

tOH

tOD

tTD

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