R5F564MFDDFB datasheet(123/162 Pages) RENESAS

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R01DS0173EJ0120 Rev.1.20

Page 123 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.7.12

SSI

Figure 2.66

Clock Input/Output Timing

Figure 2.67

Transmit/Receive Timing (SSISCKn Rising Synchronous)

Table 2.38

Serial Sound Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

SSI

AUDIO_MCLK input frequency

tAUDIO

—50

MHz

Output clock cycle

150

64000

Figure 2.66

Input clock cycle

150

64000

Clock high pulse width

tHC

—

Clock low pulse width

tLC

—

Clock rising time

tRC

—25

Data delay time

tDTR

–5

Figure 2.67,

Figure 2.68

Setup time

tSR

—

Hold time

tHTR

—

WS change edge SSIDATA output delay

tDTRW

—

Figure 2.69

SSISCKn

tHC

tLC

tRC

tI, tO

tSR

tHTR

tDTR

SSISCKn

(input or output)

SSIWSn, SSIDATAn,

SSIRXDn (input)

SSIWSn, SSIDATAn,

SSITXDn (output)

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