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R5F564MFDDFB Datasheet(PDF) 127 Page - Renesas Technology Corp |
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R5F564MFDDFB Datasheet(HTML) 127 Page - Renesas Technology Corp |
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127 / 162 page  R01DS0173EJ0120 Rev.1.20 Page 127 of 162 Oct 20, 2022 RX64M Group 2. Electrical Characteristics 2.3.7.15 ETHERC Note 1. RMII_TXD_EN, RMII_TXD1, RMII_TXD0 Note 2. RMII_CRS_DV, RMII_RXD1, RMII_RXD0, RMII_RX_ER Table 2.41 ETHERC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VCC_USBA = AVCC_USBA = 3.0 to 3.6 V, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF High-drive output is selected by the driving ability control register. Item Symbol Min. Max. Unit Test Conditions ETHERC (RMII) REF50CK cycle time Tck 20 — ns Figure 2.72 to Figure 2.74 REF50CK frequency Typ. 50 MHz — — 50 + 100 ppm MHz REF50CK duty — 35 65 % REF50CK rise/fall time Tckr/ckf 0.5 3.5 ns RMII_xxxx*1 output delay time Tco 2.5 15.0 ns RMII_xxxx*2 setup time Tsu 3— ns RMII_xxxx*2 hold time Thd 1— ns RMII_xxxx*1, *2 rise/fall time Tr/Tf 0.5 5 ns ET_WOL output delay time tWOLd 1 23.5 ns Figure 2.76 ETHERC (MII) ET_TX_CLK cycle time tTcyc 40 — ns — ET_TX_EN output delay time tTENd 1 20 ns Figure 2.77 ET_ETXD0 to ET_ETXD3 output delay time tMTDd 120 ns ET_CRS setup time tCRSs 10 — ns ET_CRS hold time tCRSh 10 — ns ET_COL setup time tCOLs 10 — ns Figure 2.78 ET_COL hold time tCOLh 10 — ns ET_RX_CLK cycle time tTRcyc 40 — ns — ET_RX_DV setup time tRDVs 10 — ns Figure 2.79 ET_RX_DV hold time tRDVh 10 — ns ET_ERXD0 to ET_ERXD3 setup time tMRDs 10 — ns ET_ERXD0 to ET_ERXD3 hold time tMRDh 10 — ns ET_RX_ER setup time tRERs 10 — ns Figure 2.80 ET_RX_ER hold time tRESh 10 — ns ET_WOL output delay time tWOLd 1 23.5 ns Figure 2.81 |
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