R5F564MFDDFB datasheet(126/162 Pages) RENESAS

126 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 126 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.7.14

SDHI

Note 1. When a letter “-A”, “-B”, etc. to indicate group membership is appended to the pin name, each pin is recommended to use in

combination with the pins in the same group. All SDHI AC timings are measured in combination with the pins in the same group.

Note 2. tPBcyc: PCLKB cycle

Figure 2.71

SD Host Interface Input/Output Signal Timing

Table 2.40

SDHI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit

Test Conditions*1

SDHI

SDHI_CLK pin output cycle time

tPP(SD)

2 × tPBcyc*2

—

Figure 2.71

SDHI_CLK pin output high pulse width

tWH(SD)

0.4 × tPP(SD)

—ns

SDHI_CLK pin output low pulse width

tWL(SD)

0.4 × tPP(SD)

—ns

SDHI_CLK pin output rise time

tTLH(SD)

—5

SDHI_CLK pin output fall time

tTHL(SD)

—5

Output data delay time (data transfer mode) for

SDHI_CMD and SDHI_D0 to SDHI_D3 pins

tODLY(SD)

–6.5

Input data setup time for SDHI_CMD and SDHI_D0 to

SDHI_D3 pins

tISU(SD)

7—

Input data hold time for SDHI_CMD and SDHI_D0 to

SDHI_D3 pins

tIH(SD)

2—

SDHI_CLK output

SDHI_CMD, SDHI_D3 to SDHI_D0 input

SDHI_CMD, SDHI_D3 to SDHI_D0 output

tWL(SD)

tWH(SD)

tPP(SD)

tISU(SD) tIH(SD)

tTLH(SD)

tTHL(SD)

tODLY(SD)

VIH

VIL

VIH

50% VCC

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