R5F564MFDDFB datasheet(125/162 Pages) RENESAS

125 / 162 page

R01DS0173EJ0120 Rev.1.20

Page 125 of 162

Oct 20, 2022

RX64M Group

2. Electrical Characteristics

2.3.7.13

MMC

Note 1. tPBcyc: PCLKB cycle

Note 2. We recommend that pins suffixed with the same letter such as -A and -B, indicating grouping of the pins, should be used as a

set. The AC characteristics of the MMC are measured using the pins from the same group.

Figure 2.70

MMC Interface

Table 2.39

MMC Host Interface Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0,

VCC_USBA = AVCC_USBA = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = VSS1_USBA = VSS2_USBA = PVSS_USBA = AVSS_USBA = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.*1

Max.

Unit

Test

Conditions*2

MMCIF

MMC_CLK clock cycle

tMMCPP

2 × tPBcyc

—

Figure 2.70

MMC_CLK clock high level width

tMMCWH

6.5

—

MMC_CLK clock low level width

tMMCWL

6.5

—

MMC_CLK clock rising time

tMMCLH

—5

MMC_CLK clock falling time

tMMCHL

—5

MMC_CMD, MMC_D7 to MMC_D0 output data delay

(data transfer mode)

tMMCODLY

–6.5

6.5

MMC_CMD, MMC_D7 to MMC_D0 input data setup

tMMCISU

8—

MMC_CMD, MMC_D7 to MMC_D0 input data hold

tMMCIH

2—

tMMCPP

tMMCWL

tMMCWH

tMMCHL

tMMCLH

tMMCISU

tMMCIH

tMMCODLY (max)

tMMCODLY (min)

MMC_CLK

MMC_CMD,

MMC_D7 to MMC_D0 input

MMC_CMD,

MMC_D7 to MMC_D0 output

R5F564MFDDFB Datasheet(PDF) 125 Page - Renesas Technology Corp

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