S7G2 datasheet(3/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 3 of 117

Sep 24, 2025

S7G2 Datasheet

1. Overview

Table 1.3

System (1 of 2)

Feature

Functional description

Operating modes

Two operating modes:

- Single-chip mode

- SCI or USB boot mode.

See section 3, Operating Modes in Userʼs Manual.

Resets

14 resets:

 RES pin reset

 Power-on reset

 Voltage monitor 0 reset

 Voltage monitor 1 reset

 Voltage monitor 2 reset

 Independent watchdog timer reset

 Watchdog timer reset

 Deep Software Standby reset

 SRAM parity error reset

 SRAM DED error reset

 Bus master MPU error reset

 Bus slave MPU error reset

 Stack pointer error reset

 Software reset.

See section 6, Resets in Userʼs Manual.

Low Voltage Detection (LVD)

The Low Voltage Detection (LVD) function monitors the voltage level input to the VCC pin, and

the detection level can be selected using a software program. See section 8, Low Voltage

Detection (LVD) in Userʼs Manual.

Clocks

 Main clock oscillator (MOSC)

 Sub-clock oscillator (SOSC)

 High-speed on-chip oscillator (HOCO)

 Middle-speed on-chip oscillator (MOCO)

 Low-speed on-chip oscillator (LOCO)

 PLL frequency synthesizer

 IDWT-dedicated on-chip oscillator

 Clock out support.

See section 9, Clock Generation Circuit in Userʼs Manual.

Clock Frequency Accuracy

Measurement Circuit (CAC)

The Clock Frequency Accuracy Measurement Circuit (CAC) counts pulses of the clock to be

measured (measurement target clock) within the time generated by the clock to be used as a

measurement reference (measurement reference clock), and determines the accuracy

depending on whether the number of pulses is within the allowable range.

When measurement is complete or the number of pulses within the time generated by the

measurement reference clock is not within the allowable range, an interrupt request is

generated. See section 10, Clock Frequency Accuracy Measurement Circuit (CAC) in Userʼs

Manual.

Interrupt Controller Unit (ICU)

The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC

module and DMAC module. The ICU also controls NMI interrupts. See section 14, Interrupt

Controller Unit (ICU) in Userʼs Manual.

Key interrupt function (KINT)

A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting

a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function

(KINT) in Userʼs Manual.

Low power modes

Power consumption can be reduced in multiple ways, including by setting clock dividers,

controlling EBCLK output, controlling SDCLK output, stopping modules, selecting power

control mode in normal operation, and transitioning to low power modes. See section 11, Low

Power Modes in Userʼs Manual.

Battery backup function

A battery backup function is provided for partial powering by a battery. The battery-powered

area includes the RTC, SOSC, backup memory, and switch between VCC and VBATT. See

section 12, Battery Backup Function in Userʼs Manual.

The register write protection function protects important registers from being overwritten

because of software errors. See section 13, Register Write Protection in Userʼs Manual.

Memory Protection Unit (MPU)

Three Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided

for memory protection. See section 16, Memory Protection Unit (MPU) in Userʼs Manual.

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