S7G2 datasheet(82/117 Pages) RENESAS

82 / 117 page

R01DS0262EU0150 Rev.1.50

Page 82 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

Figure 2.57

SSI data transmit and receive timing when SSICR.SCKP = 1

Figure 2.58

SSI data output delay after SSIWSn change

2.3.15

SD/MMC Host Interface Timing

Table 2.31

SD/MMC Host Interface signal timing

Conditions: High drive output is selected in the port drive capability bit in the PmnPFS register.

Clock duty ratio is 50%.

Parameter

Symbol

Min

Max

Unit

Test conditions

SDnCLK clock cycle

TSDCYC

Figure 2.59

SDnCLK clock high pulse width

TSDWH

6.5

SDnCLK clock low pulse width

TSDWL

6.5

SDnCLK clock rise time

TSDLH

-3

SDnCLK clock fall time

TSDHL

-3

SDnCMD/SDnDATm output data delay

TSDODLY

-6

SDnCMD/SDnDATm input data setup

TSDIS

SDnCMD/SDnDATm input data hold

TSDIH

tSR

tHTR

tDTR

SSISCKn

(Input or Output)

SSIWSn, SSIDATAn

(Input)

SSIWSn, SSIDATAn

(Output)

tDTRW

SSIWSn (input)

SSIDATAn (output)

MSB bit output delay after SSIWSn change for Slave

transmitter when DEL = 1, SDTA = 0 or DEL = 1, SDTA = 1, SWL[2:0]=DWL[2:0]

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