S7G2 datasheet(80/117 Pages) RENESAS

80 / 117 page

R01DS0262EU0150 Rev.1.50

Page 80 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

Note:

tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle.

Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE

set to 1.

Note 2. Cb indicates the total capacity of the bus line.

Figure 2.54

I2C bus interface input/output timing

Table 2.29

IIC timing (2)

Conditions:

(1) Setting of the SCL0_A, SDA0_A pins is not required with the port drive capability bit in the PmnPFS register.

Parameter

Symbol Min*1,*2

Max

Unit

Test

conditions

IIC

(Fast-mode+)

ICFER.FMPE = 1

SCL input cycle time

tSCL

6 (12) × tIICcyc + 240

Figure 2.54

SCL input high pulse width

tSCLH

3 (6) × tIICcyc + 120

SCL input low pulse width

tSCLL

3 (6) × tIICcyc + 120

SCL, SDA input rise time

tSr

120

SCL, SDA input fall time

tSf

120

SCL, SDA input spike pulse removal

time

tSP

1 (4) × tIICcyc

SDA input bus free time when

wakeup function is disabled

tBUF

3 (6) × tIICcyc + 120

SDA input bus free time when

wakeup function is enabled

tBUF

3(6) × tIICcyc + 4 × tPcyc

+ 120

-ns

Start condition input hold time when

wakeup function is disabled

tSTAH

tIICcyc + 120

START condition input hold time

when wakeup function is enabled

tSTAH

1(5) × tIICcyc + tPcyc +

120

-ns

Restart condition input setup time

tSTAS

120

Stop condition input setup time

tSTOS

120

Data input setup time

tSDAS

tIICcyc + 30

Data input hold time

tSDAH

SCL, SDA capacitive load

550

SDA0 to SDA2

SCL0 to SCL2

VIH

VIL

tSTAH

tSCLH

tSCLL

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Test conditions :

VIH = VCC × 0.7, VIL = VCC × 0.3

VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0)

VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1)

Sr*

Note 1. S, P, and Sr indicate the following:

S: Start condition

P: Stop condition

Sr: Restart condition

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