S7G2 datasheet(9/117 Pages) RENESAS

9 / 117 page

R01DS0262EU0150 Rev.1.50

Page 9 of 117

Sep 24, 2025

S7G2 Datasheet

1. Overview

1.2

Block Diagram

Figure 1.1 shows the block diagram of the MCU superset, some individual devices within the group have a subset of the

features.

Figure 1.1

Block diagram

Memory

4MB code flash

64 KB data flash

640 KB SRAM

DMA

DMAC × 8

System

Mode control

Power control

ICU

MOSC/SOSC

Clocks

(H/M/L) OCO

PLL/USBPLL

Battery backup

GPT32EH x 4

GPT32E x 4

GPT32 x 6

Timers

AGT × 2

RTC

CTSU

Arm® Cortex®-M4

DSP

FPU

MPU

NVIC

System timer

Test and DBG interface

Bus

MPU

DTC

CSC

External

SDRAM

WDT/IWDT

CAC

POR/LVD

Reset

Human machine interfaces

GLCDC

Graphics

DRW

JPEG Codec

PDC

ELC

Event link

SCE7

Security

Analog

CRC

Data processing

DOC

SRC

Communication interfaces

QSPI

USBHS

IIC × 3

SDHI × 2

ETHERC × 2

with IEEE 1588

SPI × 2

CAN × 2

SSI × 2

USBFS

SCI × 10

IrDA × 1

TSN

DAC12

ACMPHS × 6

ADC12 with

PGA × 2

8 KB Standby

SRAM

protection

KINT

Note:

Not available on all parts

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