S7G2 datasheet(98/117 Pages) RENESAS

98 / 117 page

R01DS0262EU0150 Rev.1.50

Page 98 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

2.9

POR and LVD Characteristics

Note 1. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection

levels VPOR, Vdet1, and Vdet2 for POR and LVD.

Note 2. The low-power function is disabled and DEEPCUT[1:0] = 00b or 01b.

Note 3. The low-power function is enabled and DEEPCUT[1:0] = 11b.

Figure 2.90

Power-on reset timing

Table 2.47

Power-on reset circuit and voltage detection circuit characteristics

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Voltage detection

level

Power-on reset

(POR)

Module-stop function

disabled*1

VPOR

2.5

2.6

2.7

Figure 2.90

Module-stop function

enabled*2

2.0

2.35

2.7

Voltage detection circuit (LVD0)

Vdet0_1

2.84

2.94

3.04

Figure 2.91

Vdet0_2

2.77

2.87

2.97

Vdet0_3

2.70

2.80

2.90

Voltage detection circuit (LVD1)

Vdet1_1

2.89

2.99

3.09

Figure 2.92

Vdet1_2

2.82

2.92

3.02

Vdet1_3

2.75

2.85

2.95

Voltage detection circuit (LVD2)

Vdet2_1

2.89

2.99

3.09

Figure 2.93

Vdet2_2

2.82

2.92

3.02

Vdet2_3

2.75

2.85

2.95

Internal reset time

Power-on reset time

tPOR

-4.6

Figure 2.90

LVD0 reset time

tLVD0

-0.70

Figure 2.91

LVD1 reset time

tLVD1

-0.57

Figure 2.92

LVD2 reset time

tLVD2

-0.57

Figure 2.93

Minimum VCC down time

tVOFF

200

μs

Figure 2.90,

Figure 2.91

Response delay

tdet

200

μs

Figure 2.90 to

Figure 2.93

LVD operation stabilization time (after LVD is enabled)

Td(E-A)

μs

Figure 2.92,

Figure 2.93

Hysteresis width (LVD1 and LVD2)

VLVH

-80

Internal reset signal

(active-low)

VCC

tVOFF

tdet tPOR

tdet

tPOR

tdet

VPOR

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