C167CS-4RM datasheet(33/517 Pages) INFINEON

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C167CS

Derivatives

Architectural Overview

User’s Manual

2-16

V2.0, 2000-07

General Purpose Timer (GPT) Unit

The GPT units represent a very flexible multifunctional timer/counter structure which

may be used for many different time related tasks such as event timing and counting,

pulse width and duty cycle measurements, pulse generation, or pulse multiplication.

The five 16-bit timers are organized in two separate modules, GPT1 and GPT2. Each

timer in each module may operate independently in a number of different modes, or may

be concatenated with another timer of the same module.

Each timer can be configured individually for one of four basic modes of operation, which

are Timer, Gated Timer, Counter Mode and Incremental Interface Mode (GPT1 timers).

In Timer Mode the input clock for a timer is derived from the internal CPU clock divided

by a programmable prescaler, while Counter Mode allows a timer to be clocked in

reference to external events (via TxIN).

Pulse width or duty cycle measurement is supported in Gated Timer Mode where the

operation of a timer is controlled by the ‘gate’ level on its external input pin TxIN.

In Incremental Interface Mode the GPT1 timers can be directly connected to the

incremental position sensor signals A and B via the respective inputs TxIN and TxEUD.

Direction and count signals are internally derived from these two input signals, so the

contents of timer Tx corresponds to the sensor position. The third position sensor signal

TOP0 can be connected to an interrupt input.

The count direction (up/down) for each timer is programmable by software or may

additionally be altered dynamically by an external signal (TxEUD) to facilitate e.g.

position tracking.

The core timers T3 and T6 have output toggle latches (TxOTL) which change their state

on each timer over-flow/underflow. The state of these latches may be output on port pins

(TxOUT) or may be used internally to concatenate the core timers with the respective

auxiliary timers resulting in 32/33-bit timers/counters for measuring long time periods

with high resolution.

Various reload or capture functions can be selected to reload timers or capture a timer’s

contents triggered by an external signal or a selectable transition of toggle latch TxOTL.

The maximum resolution of the timers in module GPT1 is 8 CPU clock cycles

(= 16 TCL). With their maximum resolution of 4 CPU clock cycles (= 8 TCL) the GPT2

timers provide precise event control and time measurement.

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