C167CS-4RM datasheet(25/517 Pages) INFINEON

25 / 517 page

C167CS

Derivatives

Architectural Overview

User’s Manual

2-8

V2.0, 2000-07

2.2

The On-Chip System Resources

The C167CS controllers provide a number of powerful system resources designed

around the CPU. The combination of CPU and these resources results in the high

performance of the members of this controller family.

Peripheral Event Controller (PEC) and Interrupt Control

The Peripheral Event Controller allows to respond to an interrupt request with a single

data transfer (word or byte) which only consumes one instruction cycle and does not

require to save and restore the machine status. Each interrupt source is prioritized every

machine cycle in the interrupt control block. If PEC service is selected, a PEC transfer is

started. If CPU interrupt service is requested, the current CPU priority level stored in the

PSW register is tested to determine whether a higher priority interrupt is currently being

serviced. When an interrupt is acknowledged, the current state of the machine is saved

on the internal system stack and the CPU branches to the system specific vector for the

peripheral.

The PEC contains a set of SFRs which store the count value and control bits for eight

data transfer channels. In addition, the PEC uses a dedicated area of RAM which

contains the source and destination addresses. The PEC is controlled similar to any

other peripheral through SFRs containing the desired configuration of each channel.

An individual PEC transfer counter is implicitly decremented for each PEC service

except forming in the continuous transfer mode. When this counter reaches zero, a

standard interrupt is performed to the vector location related to the corresponding

source. PEC services are very well suited, for example, to move register contents to/

from a memory table. The C167CS has 8 PEC channels each of which offers such fast

interrupt-driven data transfer capabilities.

Memory Areas

The memory space of the C167CS is configured in a Von Neumann architecture which

means that code memory, data memory, registers and IO ports are organized within the

same linear address space which covers up to 16 MBytes. The entire memory space can

be accessed bytewise or wordwise. Particular portions of the on-chip memory have

additionally been made directly bit addressable.

A 3 KByte 16-bit wide internal RAM (IRAM) provides fast access to General Purpose

Registers (GPRs), user data (variables) and system stack. The internal RAM may also

be used for code. A unique decoding scheme provides flexible user register banks in the

internal memory while optimizing the remaining RAM for user data.

C167CS-4RM Datasheet(PDF) 25 Page - Infineon Technologies AG