C167CS-4RM datasheet(55/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-5

V2.0, 2000-07

If a conditional branch is not taken, there is no deviation from the sequential program

flow, and thus no extra time is required. In this case the instruction after the branch

instruction will enter the decode stage of the pipeline at the beginning of the next

machine cycle after decode of the conditional branch instruction.

Cache Jump Instruction Processing

The C167CS incorporates a jump cache to optimize conditional jumps, which are

processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time

to fetch the branch target instruction can be saved and thus the corresponding cache

jump instruction in most cases takes only one machine cycle.

This performance is achieved by the following mechanism:

Whenever a cache jump instruction passes through the decode stage of the pipeline for

the first time (and provided that the jump condition is met), the jump target instruction is

fetched as usual, causing a time delay of one machine cycle. In contrast to standard

branch instructions, however, the target instruction of a cache jump instruction (JMPA,

JMPR, JB, JBC, JNB, JNBS) is additionally stored in the cache after having been fetched.

After each repeatedly following execution of the same cache jump instruction, the jump

target instruction is not fetched from program memory but taken from the cache and

immediately injected into the decode stage of the pipeline (see Figure 4-4).

A time saving jump on cache is always taken after the second and any further

occurrence of the same cache jump instruction, unless an instruction which, has the

fundamental capability of changing the CSP register contents (JMPS, CALLS, RETS,

TRAP, RETI), or any standard interrupt has been processed during the period of time

between two following occurrences of the same cache jump instruction.

Figure 4-4

Cache Jump Instruction Pipelining

MCT04329

FETCH

DECODE

EXECUTE

WRITEBACK

n+2

TARGET

(

INJECT)

1 Machine Cycle

1st Loop Iteration

Cache Jmp

...

TARGET+1

TARGET

Injection

(

INJECT)

Cache Jmp

n+2

TARGET+1

Repeated Loop Iteration

Cache Jmp

...

TARGET+2

TARGET+1

Injection of Cached

Target Instruction

Cache Jmp

TARGET

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