C167CS-4RM datasheet(44/517 Pages) INFINEON

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C167CS

Derivatives

Memory Organization

User’s Manual

3-7

V2.0, 2000-07

the previous context. The number of implemented register banks (arbitrary sizes) is only

limited by the size of the available internal RAM.

Details on using, switching and overlapping register banks are described in Chapter 22.

PEC Source and Destination Pointers

The 16 word locations in the internal RAM from 00’FCE0H to 00’FCFEH (just below the

bit-addressable section) are provided as source and destination address pointers for

data transfers on the eight PEC channels. Each channel uses a pair of pointers stored

in two subsequent word locations with the source pointer (SRCPx) on the lower and the

destination pointer (DSTPx) on the higher word address (x = 7 … 0).

Figure 3-4

Location of the PEC Pointers

Whenever a PEC data transfer is performed, the pair of source and destination pointers,

which is selected by the specified PEC channel number, is accessed independent of the

current DPP register contents and also the locations referred to by these pointers are

accessed independent of the current DPP register contents. If a PEC channel is not

used, the corresponding pointer locations area available and can be used for word or

byte data storage.

For more details about the use of the source and destination pointers for PEC data

transfers see Chapter 5.

00’FCE2

00’FCE0 H

SRCP0

DSTP0

00’F5FE

00’F600

MCD03903

Destination

00’FCFC

Pointers

and

PEC

Source

SRCP7

00’FCFE H

DSTP7

Internal

00’FCE0

00’FCDE

RAM

00’FCFE

00’FD00

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