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C167CS-4RM Datasheet(PDF) 63 Page - Infineon Technologies AG |
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C167CS-4RM Datasheet(HTML) 63 Page - Infineon Technologies AG |
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63 / 517 page  C167CS Derivatives The Central Processing Unit (CPU) User’s Manual 4-13 V2.0, 2000-07 The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset (see hardware effectable bits). . SYSCON System Control Register SFR (FF12H/89H) Reset Value: 0XX0H 15 14 13 12 11 10 9 876 5432 1 0 STKSZ ROM S1 SGT DIS ROM EN BYT DIS CLK EN WR CFG CS CFG - OW D DIS BD RST EN XP EN VISI BLE XPER- SHARE rw rw rw rwh rwh rw rwh rw - rwh rw rw rw rw Bit Function XPER-SHARE XBUS Peripheral Share Mode Control 0: External accesses to XBUS peripherals are disabled. 1: XBUS peripherals are accessible via the external bus during hold mode. VISIBLE Visible Mode Control 0: Accesses to XBUS peripherals are done internally. 1: XBUS peripheral accesses are made visible on the external pins. XPEN XBUS Peripheral Enable Bit 0: Accesses to the on-chip X-Peripherals and their functions are disabled. 1: The on-chip X-Peripherals are enabled and can be accessed. BDRSTEN Bidirectional Reset Enable Bit 0: Pin RSTIN is an input only. 1: Pin RSTIN is pulled low during the internal reset sequence after any reset. OWDDIS Oscillator Watchdog Disable Bit (Depending on reset configuration) 0: The on-chip oscillator watchdog is enabled and active. 1: The on-chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input. CSCFG Chip Select Configuration Control (Cleared after reset) 0: Latched CS mode. The CS signals are latched internally and driven to the (enabled) port pins synchronously. 1: Unlatched CS mode. The CS signals are directly derived from the address and driven to the (enabled) port pins. WRCFG Write Configuration Control (Set according to pin P0H.0 during reset) 0: Pins WR and BHE retain their normal function. 1: Pin WR acts as WRL, pin BHE acts as WRH. |
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