C167CS-4RM datasheet(70/517 Pages) INFINEON

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C167CS

Derivatives

The Central Processing Unit (CPU)

User’s Manual

4-20

V2.0, 2000-07

The Code Segment Pointer CSP

This non-bit addressable register selects the code segment being used at run-time to

access instructions. The lower 8 bits of register CSP select one of up to 256 segments

of 64 KBytes each, while the upper 8 bits are reserved for future use.

Code memory addresses are generated by directly extending the 16-bit contents of the

IP register by the contents of the CSP register as shown in Figure 4-5.

In case of the segmented memory mode the selected number of segment address bits

(via bitfield SALSEL) of register CSP is output on the respective segment address pins

of Port 4 for all external code accesses. For non-segmented memory mode or Single

Chip Mode the content of this register is not significant, because all code accesses are

automatically restricted to segment 0.

Note: The CSP register can only be read but not written by data operations. It is,

however, modified either directly by means of the JMPS and CALLS instructions,

or indirectly via the stack by means of the RETS and RETI instructions.

Upon the acceptance of an interrupt or the execution of a software TRAP

instruction, the CSP register is automatically set to zero.

CSP

Code Segment Pointer

SFR (FE08H/04H)

Reset Value: 0000H

9876

543210

------

SEGNR

r(w)h

Bit

Function

SEGNR

Segment Number

Specifies the code segment, from where the current instruction is to be

fetched. SEGNR is ignored, when segmentation is disabled.

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