SABRE-LL-I datasheet(67/141 Pages) STMICROELECTRONICS

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SABRE-LL-I

Power bridges

67/141

14.3.7

Regulation loop

As seen before S.A.B.Re contains 2 regulation loops for switching regulators that are used

when bridge 3 is used as a regulator. These loops are assembled using internal

comparators and filters similar to that used in main switching regulator.

When bridge 3 is not used for this purpose or when only one regulation loop is needed, the

control loop is available on a GPIO output thus enabling the customer to assembly a basic

buck switching regulator using an external Power FET. The comparators used in the above

mentioned regulation loops are general purpose low voltage (3.3 V) comparators; when the

relative regulation loop is not used they can be accessed as shown in the diagram here

below:

Vuvhys

Under voltage hysteresis

taux_uv

Under voltage deglitch

filter

5µs

Ilimit

Current limit protection

1.6

2.5

tdeglitch

Current limit deglitch

time

tI_lim

Current limit response

time

In normal operating

mode (no UV)(5)

700

tI_limUV

Current limit response

time in UV condition.

When in Under

Voltage(6)

500

Switching output rise

time

VSupply = 36V, Resistive

load to gnd: R=422

Ω(7)

530

Switching output fall time

VSupply = 36V, Resistive

load to gnd = 10

Ω(7)

tdead

Crossover dead time

100

FregPwm

Operating frequency

Fosc/64

kHz

The external components connected to the pin must be chosen to avoid that the voltage exceeds this

operative range.

The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb.

The choice of proper values for L and C depends from the application.

Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage

(VSW_main_FB).

This condition is intended to simulate an extra current on output.

This condition is intended to simulate a short circuit on output.

Rise time is measured between 10% and 90% of supply voltage.

Table 46.

Operating specification (continued)

Parameter

Description

Test condition

Min

Typ

Max

Unit

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