SABRE-LL-I datasheet(29/141 Pages) STMICROELECTRONICS

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SABRE-LL-I

Start-up configurations

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8.4

Slave device mode

In slave device mode, S.A.B.Re consider the nAWAKE pin as an input enable. Since this is

now a digital pin, the current pull up source inside the nAWAKE circuit is disabled.

At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT

seconds, S.A.B.Re enters directly in the “Low Power mode”; when nAWAKE pin is pulled

high for a period higher than tAWAKEFILT seconds, S.A.B.Re begins its start up procedure.

8.5

Master device mode

In master device mode, S.A.B.Re begins its start up procedure without waiting for any

external enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices.

During the whole start up time, it forces its GPIO[5] pin at logic level “0” in order to maintain

all slave devices in “Low Power mode” as previously described. When start up operations

are completed, S.A.B.Re forces the GPIO[5] output to logic level “1” to enable the slave

devices and keeps GPIO[5] output at high level until it senses an under-voltage on any of its

System regulators. If firmware writes in the PwrCtrl register to set Master S.A.B.Re in “Low

Power mode” it immediately forces GPIO[5] output to logic level “0” to force the slave

devices to enter in “Low Power mode”, then it waits for TMASTWAIT time and it starts its “Low

Power mode” sequence.

8.6

Single device mode

In single device mode, the device behaves similarly to master device mode but:

It doesn’t use the GPIO[5] pin to drive slave devices.

It doesn’t wait for TMASTWAIT before entering in “Low Power mode”.

8.7

Sub-configurations for slave, master or single device modes

Each slave, master or single device modes can be divided in other minor modes depending

on the start-up sequence needed for S.A.B.Re internal regulators.

Unless otherwise specified, in all the following modes the regulators included in the start up

sequence are considered system regulators and they start in the sequence indicated.

8.7.1

Bridge mode

In this configuration bridges 3 and 4 are not used as regulators and therefore can be

configured by the firmware in any of their possible bridge modes.

When in this mode the power-up sequence is:

Main switching regulator (VMAIN_SW).

Main linear regulator (VMAIN_LIN).

8.7.2

Primary regulator mode (KP)

In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as

two separate synchronous switching regulators. The last regulator in the sequence

(VAUX2_SW).is not considered a system regulator.

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