SABRE-LL-I datasheet(47/141 Pages) STMICROELECTRONICS

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SABRE-LL-I

Power bridges

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Power bridges

14.1

Overview

S.A.B.Re includes four H bridge power outputs (each one made by two independent half

bridges) that are configurable in several different configurations.

Each half bridge is protected against: over-current, over-temperature and short circuit to

ground, to supply or across the load. When an over current event occurs, all outputs are

turned off (after a filter time), and the over current bit is stored in the internal status register

that can be read through SPI.

Positive and negative voltage spikes, which occur when switching inductive loads, are

limited by integrated freewheeling diodes (see Figure 12).

Figure 12.

H Bridge block diagram

During the start up procedure the bridges are in high impedance and after that they can be

enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the

bridges return in their start-up condition and they need to be re-enabled from the micro

controller.

The bridges can use PWM signals internally generated or externally provided (supplied

through the GPIO pins). Internally generated PWM signals will run at approximately

31.25kHz with a duty cycle that, through serial interface, can be programmed and

incremented in steps of 1/(512*Fosc). To reduce the peak current requested from supply

voltage when all bridges are switching, the four internally generated PWM signals are out-

of-phase.

Each half bridge will use the PWM signal selected by the respective

MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if

High side Driver

Low side Driver

Control Logic

High side Driver

Low side Driver

Control Logic

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