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M66596FP Datasheet(PDF) 85 Page - Renesas Technology Corp |
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M66596FP Datasheet(HTML) 85 Page - Renesas Technology Corp |
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85 / 131 page ![]() M66596FP/WG rev .1.00 2006.3.14 page 85 of 127 3.4.4.2 Timing at which the FIFO port can be accessed after reading/writing has been completed when using a double buffer Figure 3.24 shows the timing at which, when using a pipe with a double buffer, the other buffer can be accessed after reading from or writing to one buffer has been completed. When using a double buffer, access to the FIFO port should be carried out after waiting 300 ns after the access made just prior to toggling. The same timing applies when a short packet is being sent based on the “BVAL=1” setting using the IN direction pipe. Indefinite WR_N / RD_N CURPIPE FRDY DTLN max 300ns min 20ns PIPE-A Buffer-A Buffer-A Buffer-B Buffer-B Access just prior to buffer toggling Figure 3.24. Timing at which the FRDY and DTLN bits are determined after reading from or writing to a double buffer has been completed |
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