M66596FP datasheet(31/131 Pages) RENESAS

31 / 131 page

M66596FP/WG

rev .1.00

2006.3.14

page 31 of 127

<<Note>>

None in particular

Interrupt enabled register 1[INTENB1]

<Address: 32H>

BCHGE

DTCHE

SIGNE SACKE

BRDYM

INTL

PCSE

Bit

Name

Function

S/W

H/W

Note

15 Nothing is placed here. These should be fixed at “0”.

14 BCHGE

USB bus change interrupt enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.4

2.7.8

3.2.11

13 Nothing is placed here. This should be fixed at “0”.

12 DTCHE

Full-Speed detach detect interrupt

enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.5

3.2.12

*1), *2)

11-6 Nothing is placed here. This should be fixed at “0”.

SIGNE

Setup transaction error detect interupt

enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.6

3.2.14

*1)

SACKE

Setup transaction complete interrupt

enabled

0: Interrupt output disabled

1: Interrupt output enabled

R/W

2.7.1

2.7.7

3.2.13

*1)

Nothing is placed here. This should be fixed at “0”.

BRDYM

BRDY interrupt status clear timing control

0: Software clears BRDY interrupt status

1: The controller clears BRDY interrupt status

R/W

*3)

INTL

Interrupt output sensing control

0: Edge sensing

1: Level sensing

R/W

3.2.1

PCSE

returning fact selection from low-power

sleep mode

0: USB resume detectionm, VBUS interrupt

detection during suspend, or CS_N signal

input

1: USB resume detectionm, or VBUS interrupt

detection during suspend

R/W

*4)

<<Notes>>

*1) DTCHE, SIGNE, SACKE bit are effective only at the time of a Host mode.

*2) The DTCHE bit is effective only at the time of Full-Speed mode.

Please perform detach detection by S/W, such as detecting ignore packet from peripheral device at the time of

Hi-Speed mode.

*3) When software sets "BRDYM=1", it will set “INTL=1” also.

*4) PCSE bit shoud be set after “USBE=1” setting.

M66596FP Datasheet(PDF) 31 Page - Renesas Technology Corp

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