AFE5804 datasheet(45/60 Pages) TI

45 / 60 page

High-Level RESET

(1.4Vto3.6V)

High-Level CS

(1.4Vto3.6V)

DeviceReadyfor

SerialRegisterWrite

DeviceReadyfor

DataConversion

StartofClock

AVDD1

AVDD2

DVDD

AVDD 5V

LVDD

ADS_RESET

FCLK

(3.3V,5.0V)

(1.8V)

VCA_PD,ADC_PD

(2)

DeviceFully

PowersDown

DeviceFully

PowersUp

1 s

(1)

WAKE

AFE5804

www.ti.com ................................................................................................................................................ SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008

RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING(1)

µs < t

1 < 50ms, 10µs < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100µs.

(1) The AVDDx and LVDD power-on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations apply while shutting

down the device.

POWER-DOWN TIMING

Power-up time shown is based on 1

µF bypass capacitors on the reference pins. t

WAKE is the time it takes for the device to wake up

completely from power-down mode. The AFE5804 has two power-down modes: complete power-down mode and partial power-down mode.

(1) tWAKE ≤ 50µs for complete power-down mode. tWAKE ≤ 2µs for partial power-down mode (provided the clock is not shut off during

power-down).

(2) The ADS_PD pins can be configured for partial power-down mode through a register setting.

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