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AFE5804 Datasheet(PDF) 30 Page - Texas Instruments |
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AFE5804 Datasheet(HTML) 30 Page - Texas Instruments |
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30 / 60 page ![]() D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK SDATA DatalatchedonrisingedgeofSCLK StartSequence EndSequence t 6 t 4 t 2 t 7 t 3 t 5 t 1 Internally-Generated VCA Control Signals D0 D39 VCA_SDATA VCA_SCLK AFE5804 SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com SERIAL INTERFACE TIMING AFE5804 PARAMETER DESCRIPTION MIN TYP MAX UNIT t1 SCLK period 50 ns t2 SCLK high time 20 ns t3 SCLK low time 20 ns t4 Data setup time 5 ns t5 Data hold time 5 ns t6 CS fall to SCLK rise 8 ns t7 Time between last SCLK rising edge to CS rising edge 8 ns VCA_SCLK and VCA_SDATA signals are generated if: • Registers with address 16, 17, or 18 (hex) are written to, and • EN_SM pin is HIGH 30 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): AFE5804 |
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