AFE5804 datasheet(54/60 Pages) TI

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CLOCK INPUT

5kW

VCM

CLKP

CLKM

VCM

CLKP

CLKM

DifferentialSine-Wave,

PECL,orLVDSClockInput

0.1 F

CLKP

CLKM

CMOSSingle-Ended

Clock

CLKP

CLKM

CMOSClockInput

0.1 F

AFE5804

SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com

The eight channels on the device operate from a

single clock input. To ensure that the aperture delay

and jitter are the same for all channels, the AFE5804

uses a clock tree network to generate individual

sampling clocks to each channel. The clock paths for

all the channels are matched from the source point to

the sampling circuit. This architecture ensures that

the performance and timing for all channels are

identical. The use of the clock tree for matching

introduces an aperture delay that is defined as the

delay between the rising edge of FCLK and the actual

instant of sampling. The aperture delays for all the

channels are matched to the best possible extent. A

mismatch of ±20ps (±3

σ) could exist between the

aperture instants of the eight ADCs within the same

Figure 104. Internal Clock Buffer

chip. However, the aperture delays of ADCs across

two

different

chips

can

several

hundred

picoseconds apart.

The

AFE5804

can

operate

either

CMOS

single-ended clock mode (default is DIFF_CLK = 0)

or differential clock mode (SINE, LVPECL, or LVDS).

In the single-ended clock mode, CLKM must be

forced to 0VDC, and the single-ended CMOS applied

on the CLKP pin. Figure 103 shows this operation.

Figure 105. Differential Clock Driving Circuit

(DIFF_CLK = 1)

Figure 103. Single-Ended Clock Driving Circuit

(DIFF_CLK = 0)

When configured for the differential clock mode

(register bit DIFF_CLK = 1) the AFE5804 clock inputs

Figure 106. Single-Ended Clock Driving Circuit

can be driven differentially (SINE, LVPECL, or LVDS)

When DIFF_CLK = 1

with little or no difference in performance between

them,

with

single-ended

(LVCMOS).

The

For best performance, the clock inputs must be

common-mode voltage of the clock inputs is set to

driven

differentially,

reducing

susceptibility

VCM using internal 5k

Ω resistors, as shown in

common-mode

noise.

For

high

input

frequency

Figure

104.

This

method

allows

using

sampling, it is recommended to use a clock source

transformer-coupled drive circuits for a sine wave

with very low jitter. Bandpass filtering of the clock

clock or ac-coupling for LVPECL and LVDS clock

source can help reduce the effect of jitter. If the duty

sources, as shown in Figure 105 and Figure 106.

cycle deviates from 50% by more than 2% or 3%, it is

When operating in the differential clock mode, the

recommended to enable the DCC through register bit

single-ended CMOS clock can be ac-coupled to the

EN_DCC.

CLKP input, with CLKM connected to ground with a

0.1

µF capacitor, as Figure 106 shows.

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