AFE5804 datasheet(31/60 Pages) TI

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SERIAL REGISTER MAP

AFE5804

www.ti.com ................................................................................................................................................ SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008

Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1)(2)(3)(4)

ADDRESS

IN HEX

D15

D14

D13

D12

D11

D10

NAME

DESCRIPTION

DEFAULT

S_RST

Self-clearing software RESET.

Inactive

RES_

VCA

VCA_SDATA

D5 = 1

See Table 4 information

<0:15>

(TGC mode)

VCA_SDATA

See Table 4 information

<16:31>

VCA_DATA

See Table 4 information

<32:39>

Channel-specific ADC

PDN_CH<1:4>

Inactive

power-down mode.

Channel-specific ADC

PDN_CH<8:5>

Inactive

power-down mode.

Partial power-down mode (fast

PDN_PARTIAL

Inactive

recovery from power-down).

PDN_COMPLETE

Inactive

power-down (slower recovery).

Configures the PD pin for

Complete

PDN_PIN_CFG

partial power-down mode.

power-down

LVDS current drive

ILVDS_LCLK<2:0>

programmability for LCLKM

3.5mA drive

and LCLKP pins.

LVDS current drive

ILVDS_FRAME

programmability for FCLKM

3.5mA drive

<2:0>

and FCLKP pins.

LVDS current drive

ILVDS_DAT<2:0>

programmability for OUTM and

3.5mA drive

OUTP pins.

Enables internal termination

Termination

EN_LVDS_TERM

for LVDS buffers.

disabled

Programmable termination for

Termination

TERM_LCLK<2:0>

LCLKM and LCLKP buffers.

disabled

TERM_FRAME

Programmable termination for

Termination

<2:0>

FCLKM and FCLKP buffers.

disabled

Programmable termination for

Termination

TERM_DAT<2:0>

OUTM and OUTP buffers.

disabled

Channel-specific,

LFNS_CH<1:4>

low-frequency noise

Inactive

suppression mode enable.

Channel-specific,

LFNS_CH<8:5>

low-frequency noise

Inactive

suppression mode enable.

Enables a repeating full-scale

EN_RAMP

Inactive

ramp pattern on the outputs.

Enables the mode wherein the

DUALCUSTOM_

output toggles between two

Inactive

PAT

defined codes.

Enables the mode wherein the

SINGLE_CUSTOM

output is a constant specified

Inactive

_PAT

code.

2MSBs for a single custom

BITS_CUSTOM1

pattern (and for the first code

Inactive

<11:10>

of the dual custom pattern).

<11> is the MSB.

BITS_CUSTOM2

2MSBs for the second code of

Inactive

<11:10>

the dual custom pattern.

10 lower bits for the single

BITS_CUSTOM1

custom pattern (and for the

Inactive

<9:0>

first code of the dual custom

pattern). <0> is the LSB.

10 lower bits for the second

BITS_CUSTOM2

code of the dual custom

Inactive

<9:0>

pattern.

(1)

The unused bits in each register (identified as blank table cells) must be programmed as '0'.

(2)

X = Register bit referenced by the corresponding name and description (default is 0).

(3)

Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.

(4)

Multiple functions in a register should be programmed in a single write operation.

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