AFE5804 datasheet(56/60 Pages) TI

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POWER SUPPLIES

GROUNDING AND BYPASSING

AFE5804

SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008 ................................................................................................................................................ www.ti.com

Table 19. State of Reference Voltages for Various Combinations of PD and INT/EXT

INTERNAL BUFFER STATE

INT/EXT

EXT_REF_VCM

REFT buffer

3-state

2.5V

3-state

2.5V(1)

1.5V + VCM/1.5V

Do not use

2.5V(1)

Do not use

REFB buffer

3-state

0.5V

3-state

0.5V(1)

1.5V – VCM/1.5V

Do not use

0.5V(1)

Do not use

VCM pin

1.5V

Force

Do not use

Force

Do not use

(1)

Weakly forced with reduced strength.

All bypassing and power supplies for the AFE5804

should be referenced to this analog ground plane. All

supply pins should be bypassed with 0.1

µF ceramic

The AFE5804 operates on three supply rails: a digital

chip capacitors (size 0603 or smaller). In order to

1.8V supply, and the 3.3V and 5V analog supplies. At

minimize

the

lead

and

trace

inductance,

the

initial power-up, the part is operational in TGC mode,

capacitors should be located as close to the supply

with

the

registers

the

respective

default

pins as possible. Where double-sided component

configurations (see Table 2).

mounting is allowed, these capacitors are best placed

In TGC mode, only the VCA (attenuator) draws a low

directly under the package. In addition, larger bipolar

current (typically 7mA) from the 5V supply. Switching

decoupling capacitors (2.2

µF to 10µF, effective at

into the CW mode, the internal V/I-amplifiers are then

lower frequencies) may also be used on the main

powered from the 5V rail as well, raising the

supply pins. These components can be placed on the

operating current on the 5V rail. At the same time, the

PCB in proximity (< 0.5in or 12.7mm) to the AFE5804

post-gain amplifiers (PGA) are being powered down,

itself.

thereby reducing the current consumption on the 3.3V

The AFE5804 internally generates a number of

rail (refer to the Electrical Characteristics table for

reference voltages, such as the bias voltages (VB1

details on TGC mode and CW mode current

through VB6). Note that in order to achieve optimal

consumption).

low-noise

performance,

the

VB1

must

All analog supply rails for the AFE5804 should be low

bypassed with a capacitor value of at least 1

µF; the

noise, including the 3.3V digital supply DVDD that

recommended value for this bypass capacitor is

connects to the internal logic blocks of the VCA within

2.2

µF. All other designed reference pins can be

the AFE5804. It is recommended to tie the DVDD

bypassed with smaller capacitor values, typically

pins to the same 3.3V analog supply as the AVDD1/2

0.1

µF. For best results choose low-inductance

pins, rather than a different 3.3V rail that may also

ceramic chip capacitors (size 402) and place them as

provide power to other logic device in the system.

close as possible to the device pins as possible.

Transients and noise generated by those devices can

High-speed mixed signal devices are sensitive to

couple into the AFE5804 and degrade overall device

various types of noise coupling. One primary source

performance.

of noise is the switching noise from the serializer and

the output buffer/drivers. For the AFE5804, care has

been taken to ensure that the interaction between the

The AFE5804 distinguishes between three different

analog and digital supplies within the device is kept to

grounds: AVSS1 and AVSS2 (analog grounds), and

a minimal amount. The extent of noise coupled and

LVSS (digital ground). In most cases, it should be

transmitted from the digital and analog sections

adequate to lay out the printed circuit board (PCB) to

depends on the effective inductances of each of the

use a single ground plane for the AFE5804. Care

supply and ground connections. Smaller effective

should be taken that this ground plane is properly

inductance of the supply and ground pins leads to

partitioned

between

various

sections

within

the

improved noise suppression. For this reason, multiple

system to minimize interactions between analog and

pins are used to connect each supply and ground

digital

circuitry.

Alternatively,

the

digital

(LVDS)

sets. It is important to maintain low inductance

supply set consisting of the LVDD and LVSS pins can

properties throughout the design of the PCB layout by

be placed on separate power and ground planes. For

use of proper planes and layer thickness.

this configuration, the AVSS and LVSS grounds

should be tied together at the power connector in a

star layout.

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