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LVDS OUTPUT TIMING CHARACTERISTICS

(1) (2)

LVDS OUTPUT TIMING CHARACTERISTICS

(1) (2)

AFE5804

www.ti.com ................................................................................................................................................ SBOS442A – JUNE 2008 – REVISED SEPTEMBER 2008

Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +85°C, sampling

frequency = as specified, CLOAD = 5pF

(3), I

OUT = 3.5mA, RLOAD = 100Ω

(4), and no internal termination, unless otherwise noted.

AFE5804

40MSPS

50MSPS

PARAMETER

TEST CONDITIONS

(5)

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

tSU

Data setup time

(6)

Data valid

(7) to zero-crossing of LCLKP

0.67

0.47

Zero-crossing of LCLKP to data becoming

Data hold time

(6)

0.85

0.65

invalid

(7)

Input clock (FCLK) rising edge cross-over to

tPROP

Clock propagation delay

16.6

12.5

14.1

output clock (FCLKP) rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle

45.5

53.5

(LCLKP – LCLKM)

Bit clock cycle-to-cycle jitter

250

ps, pp

Frame clock cycle-to-cycle jitter

150

ps, pp

Rise time is from –100mV to +100mV

tRISE, tFALL

Data rise time, data fall time

0.09

0.2

0.4

0.09

0.2

0.4

Fall time is from +100mV to –100mV

tCLKRISE,

Output clock rise time, output

Rise time is from –100mV to +100mV

0.09

0.2

0.4

0.09

0.2

0.4

tCLKFALL

clock fall time

Fall time is from +100mV to –100mV

(1)

All characteristics are at the maximum rated speed for each speed grade.

(2)

Timing parameters are ensured by design and characterization; not production tested.

(3)

CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(4)

IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(5)

Measurements are done with a transmission line of 100

Ω characteristic impedance between the device and the load.

(6)

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7)

Data valid refers to a logic high of +100mV and a logic low of –100mV.

Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +85°C, sampling

frequency = as specified, CLOAD = 5pF

(3), I

OUT = 3.5mA, RLOAD = 100Ω

(4), and no internal termination, unless otherwise noted.

AFE5804

30MSPS

20MSPS

10MSPS

PARAMETER

TEST CONDITIONS

(5)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

Data valid

(7) to zero-crossing of

tSU

Data setup time

(6)

0.8

1.5

3.7

LCLKP

Zero-crossing of LCLKP to data

Data hold time

(6)

1.2

1.9

3.9

becoming invalid

(7)

Input clock (FCLK) rising edge

tPROP

Clock propagation delay

cross-over to output clock (FCLKP)

9.5

13.5

17.3

9.5

14.5

17.3

14.7

17.1

rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle

46.5

(LCLKP – LCLKM)

Bit clock cycle-to-cycle

250

750

ps, pp

jitter

Frame clock cycle-to-cycle

150

500

ps, pp

jitter

tRISE,

Data rise time, data fall

Rise time is from –100mV to +100mV

0.09

0.2

0.4

0.09

0.2

0.4

0.09

0.2

0.4

tFALL

time

Fall time is from +100mV to –100mV

tCLKRISE,

Output clock rise time,

Rise time is from –100mV to +100mV

0.09

0.2

0.4

0.09

0.2

0.4

0.09

0.2

0.4

tCLKFALL

output clock fall time

Fall time is from +100mV to –100mV

(1)

All characteristics are at the speeds other than the maximum rated speed for each speed grade.

(2)

Timing parameters are ensured by design and characterization; not production tested.

(3)

CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(4)

IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(5)

Measurements are done with a transmission line of 100

Ω characteristic impedance between the device and the load.

(6)

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7)

Data valid refers to a logic high of +100mV and a logic low of –100mV.

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