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R5F2L3ACBNFP Datasheet(PDF) 86 Page - Renesas Technology Corp |
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R5F2L3ACBNFP Datasheet(HTML) 86 Page - Renesas Technology Corp |
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86 / 848 page  5. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 50 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group Figure 5.3 Reset Sequence Activation time of flash memory (CPU clock × 148 cycles) 0FFFCh 0FFFEh 0FFFDh Content of reset vector CPU clock Address (internal address signal) Notes: 1. Hardware reset. 2. When the low-level input width of the RESET pin is set to fOCO-S clock × 8 cycles or more, the RESET pin is driven high at the same time as the internal reset signal is held high. CPU clock × 28 cycles fOCO-S clock × 32 cycles (2) fOCO-S Internal reset signal RESET pin 10 µs or more required (1) |
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