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R5F2L3ACBNFP Datasheet(PDF) 92 Page - Renesas Technology Corp |
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R5F2L3ACBNFP Datasheet(HTML) 92 Page - Renesas Technology Corp |
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92 / 848 page ![]() 5. Resets REJ09B0441-0010 Rev.0.10 Jul 30, 2008 Page 56 of 809 Under development Preliminary specification Specifications in this manual are tentative and subject to change. R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group, R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group 5.3 Power-On Reset Function When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the pins, CPU, and SFRs are reset. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8 VCC or above. When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held high and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no division is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the status of the SFRs after power-on reset. After power-on reset, voltage monitor 0 reset is enabled when the LVDAS bit in the OFS register is set to 0 (voltage monitor 0 reset enabled after reset). Figure 5.6 shows an Example of Power-On Reset Circuit and Operation. Figure 5.6 Example of Power-On Reset Circuit and Operation RESET VCC 4.7 k Ω (reference) Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 2. Refer to 36. Electrical Characteristics. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0, bits VW0C0 and VW0C6 in the VW0C register to 1 individually, and the VCA25 bit in the VCA2 register to 1. Vdet0 Vpor1 Internal reset signal (low valid) tw(por1) Vccmin External Power VCC trth trth 1 fOCO-S × 32 1 fOCO-S × 32 |
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